Simulation and Computation of the Asymmetry of a Clocked Balanced Tunnel-Diode Comparator

摘要

By means of simulation and computation, a clocked balanced tunnel-diode comparator, in which the clock signal conditioner is also a tunnel diode, is studied. Simulation and computation of the tunnel-diode asymmetry required for obtaining a minimum offset of the zero level of the compensation voltage are carried out. Simulation of the clocked balanced comparator is performed by means of the Tanner T-Spice program.