Phase comparator insensitive to clock asymmetry

摘要

A phase comparator generates a reference pulse signal equal in duration to one bit cell, and a variable pulse having a duration representative of the duration and time displacement of the leading edge of a data pulse from the centre of the bit cell. The phase comparator includes the two D-type flip-flops (Q1,Q2) arranged so that the variable pulse is initiated by the leading edge of the data pulse in the one bit cell, the reference pulse is initiated by the edge of the clock pulse at the end of the one bit cell, and both pulses are terminated by the edge of the clock pulse at the end of the next bit cell. Hence, only clock edges at the bounds of the bit cell affect the pulse durations and the comparator is insensitive to clock asymmetry. A charge pump associated with the phase comparator provides a pump down signal amplitude equal to 3/2 the pump up signal amplitude to correct the relationship that the variable pulse (which generates the pump up signal) is 3/2 the duration of the reference pulse (which generates the pump down signal) where the data pulse edge is nominally in the centre of the bit cell.