Suppression for threshold voltage fluctuation due to SOI thickness variation in fully-depleted SOI MOSFETs

摘要

A novel back gate engineering to suppress threshold voltage fluctuation due to SOI thickness variation in fully-depleted SOI MOSFETs is proposed. This engineering requires thin buried oxide and back gate bias to make the back interface of SOI films weakly accumulated. The effectiveness of the proposed structure is theoretically predicted and experimentally verified. Application of back gate bias is a better way to suppress short channel effects than the increase in the channel doping under a constant value of threshold voltage. It is shown that the proposed structure can minimize the fluctuation of threshold voltage down to 50nm of gate length.