A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simulataneous read and write operation

摘要

A 16 MB cache DRAM LSI chip with internal 35.8 GB/s memory bandwidth and 9.0 ns of DRAM random access latency is developed targeting to be used in high-end computer applications. The floorplan, which locates I/O buffers in the internal area of the chip, minimizes the wire length between I/O buffers and DRAM macros, which is delay critical. Chip size was reduced by implementation of multi-bit flip-flops. We developed on-chip decoupling capacitors utilizing the DRAM storage node capacitor to suppress high frequency simultaneous switching noises. A prototype LSI was fabricated using 0.2μm merged logic DRAM process technology.