A Holistic Approach on Junctionless Dual Material Double Gate (DMDG) MOSFET with High k Gate Stack for Low Power Digital Applications

摘要

The 2D analytical models for electrostatic potential, threshold voltage, subthreshold swing, Drain Induced Barrier Lowering (DIBL) and drain current of the Dual Material Double Gate junctionless transistor with high k gate structure is revealed. The electric field is obtained by solving Poisson equation with the help of parabolic approximation technique. The high k gate stack engineered (JL DMDG stack MOSFET) exaggerate the I-ON current of 10(-4) (A/mu m) and I-OFF current of 10(-14)(A/mu m) gives a remarkable amount of leakage current reduction. The short channel effects are quashed with the symmetric high k gate stack structure to a good extent. The device characteristics have been analyzed for various different high k materials. The significant outcomes of analytical solutions are mapped with the numerical solutions from Synopsys TCAD device simulator to affirm and validate the device structure. The JL DMDG Stack MOSFET based inverter circuit was also implemented to empower the device performance in digital applications. The voltage transfer characteristics, noise margin, delay and power dissipation of the JL DMDG stack MOSFET inverter circuit is assessed through numerical simulator with the help of Verilog-A language show substantial improvement due to this gate stack engineering model.