Simulation Study on Scalability Improvement of Logic Transistors with MoS_2 Channel and N+/P+ Si Tunnel Junction

摘要

This paper presents the proposal of hybrid device structure using MoS_2 layer and Tunnel FET (TFET) on SOI substrate to improve the scalability of logic transistors for sub-0.5V application based on simulation works. The proposed hybrid device has a MoS_2 layer as the channel and N+/P+ Si junction at the source edge to provide the heterogeneous structure of two-dimensional (2D) FET and TFET devices. It has been observed that the proposed device shows the reasonable DIBL (Drain-Induced Barrier Lowering) of 50mV even for 10nm gate length. In particular, the proposed devices have the subthreshold slope of 32mV/dec @10nm gate length) by applying N+/P+ Si tunnel junction at the source side. Also, the proposed hybrid FET with gate length of 4nm is demonstrated to threshold voltage of 0.1V and reasonable Ioff of 300nA/um @Vds of 0.5V by applying extremely thin MoS_2 channel of 1nm.