Simulation Study of the Double-Gate Tunnel Field-Effect Transistor with Step Channel Thickness

摘要

2D schematic diagram of the SC TFET, si1, and si2 are the channel thickness near the source region and the drain region, the asymmetry between the source and drain is obviously introduced. Cutline AA’ is the cutline along the horizontal direction. The vertical distance between the cutline and the surface of source region is 0.5 nm. Transfer curves of the SC TFET and the conventional DG TFETs in log and linear scale