Low-temperature electrical characterization of fully depleted eXtra-strained SOI n-MOSFETs with TiN/Hf0_2 gate stack for the 32-nm technology node

摘要

In this paper, experimental results for low-temperature operation on advanced eXtra-strained FD-SOI NMOS transistors with thin film, high-k dielectric, mid-gap metal gate, and with very aggressive dimensions are presented for the 32-nm technology node. The temperature dependence of some key parameters are used to analyze the impact of strain amount on the stress-induced mobility gain, to identify the major physical mechanisms responsible of this enhanced performance, as well as the short channel effect and the narrow channel effect, down to 25 nm gate length and width.