Hot-carrier effects in n-channel low-temperature poly-Si TFTs

摘要

Degradation due to hot-carrier effects of LDD structured TFTs has been compared with that of SD (single drain) ones. It is found that both ΔGmmax and ΔVt shows the maximum at the stress gate voltage which coincide with the gate voltage showing the maximum substrate current and degradation of ΔGmmax at the stress bias is 10% of initial value, which is 1/8 of SD structured TFTs. Furthermore, both ΔGmmax and ΔVt of LDD and SD devices exhibit a power-time dependence with a slop of around 0.5 at short time stress and around 0.2 for long time stress, which means that degradation for short stress time is mainly caused by creation of interface state at the Si-SiO{sub}2 interface and/or poly-Si grain boundary and that for long stress time is caused by the generation of electron traps in gate oxide and/or grain boundary.