The C-R method used for L{sub}(eff) extraction and process optimization in nano N/P-MOSFET's devices

摘要

In this paper, a modified C-V method (C-R method) is adopted to improve the nano-MOSFET device performance by optimizing the S/D engineering. Using the C-R method (the Capacitance-Ratio method), more consistent and reasonable L{sub}(eff) can be extracted and the process bias (including L{sub}(ovlap) and L{sub}(pb)) can be exactly measured for the N/PMOS devices with halo and Ge implant process. Comparing the I-V data, those parameters can be used to analysis device characteristics under various S/D engineering conditions, and then can be used to help optimizing the nano-MOSFET devices.