A study of the method of reducing the gain error of a high-precision pipelined A/D converter with element mismatching

摘要

Although a pipelined A/D converter has features of realizing a high-speed operation and achieving a small circuit size, the element mismatch strongly affects its performance. The element mismatch introduces errors at the A/D output and deteriorates the dynamic range. In this paper, we proposed a new conversion method that is not affected by element mismatches and that reduces the gain error of a pipelined A/D converter. This has been done by taking two output signals, that appear in turn in every clock cycle with equal amount but with opposite polarity of the mismatch error, and by averaging these two. It is acturlly verified by the simulation by using C language. As a result, it is confirmed that the gain error decreased.