Two orders of magnitude leakage power reduction of low voltage SRAM's by row-by-row dynamic VDD control (RRDV) scheme

摘要

A novel SRAM scheme is proposed that can reduce the active leakage power by two orders of magnitude. In 10W voltage region less than 1V, the VTH, V{sub}(TH), is lowered to less than 0.2V and leakage power of memory cells becomes a dominant issue. By dynamically dropping the supply voltage of un-accessed cells row by row, the cell leakage can be reduced exponentially through the Drain Induced Barrier Lowering (DIBL) effect. Additionally, to lower the leakage from bit-line through transfer gates of memory cells, un-accessed word line is applied negative voltage together with reduced swing write technique. The basic advantage is verified by measurement and the effectiveness in future generations is discussed by simulations.