Low Leakage Current CMOS SRAM

摘要

The growing demands in the multimedia rich applications are motivating the low-power and high-speed circuit designer to work more closely towards the design issues arising from the design trade-offs in power and speed. This paper targets the modeling and simulation of CMOS leakage currents and its minimization approach to reduce the power consumption by a single cell SRAM cache. Utilizing separate bit line and word line during read operation decouples the other cell node from the bit line, hence, enhancing the read static noise margin (SNM) by almost 2 times as compared to the conventional 6T SRAM.