A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis Under Effective Channel-Length Variation

摘要

As the fabrication process technology is moving from submicron region to deep submicron or nanometer region, the impact of process parameter variations is becoming more and more dominant and increasing the loss in parametric yield due to variation in leakage power and delay. As a consequence, parametric yield loss has become a serious concern of the fabrication houses. This has opened up a challenge to the designers' community to design circuits that are tolerant to process parameter variations, thereby increasing the parametric yield. In this paper, we have proposed a novel approach by judicious use of sizing along with single-V_t realization to achieve reduction in leakage power comparable to dual-V_t based approaches, but having less sensitivity to process parameter variations. The effect of statistical variation of effective channel length on delay and leakage power have been studied and compared using Monte-Carlo simulation. The simulation results indicate that the proposed approach provides better reduction in delay and leakage variabilities and also provides higher parametric yield compared to existing representative dual-V_t based approaches with comparable reduction in total and leakage power.