Study of Resist Strip Chemistries for Ultra Low-k/Cu Interconnect

摘要

New generation of integrated circuits requires the introduction of ultra low-k dielectric material (k < 2,5) to reduce the RC delay. One of the challenges in integrating these ultra low-k materials is the susceptibility of porous dielectric materials to the post etch resist stripping and residue clean processes. There have been studies comparing the effect of oxidization and reducing chemistries to the ultra low-k materials in a conventional asher [1], There has also been report on the approach of using directional ashing to avoid damage to the ultra low-k materials [2], In order to gain further understanding regarding the effect of oxidizing vs. reducing chemistries, ion vs. radicals, pressure and temperature to the low-k materials (both dense and porous), we have started a comprehensive study to find answers to these questions. This paper is to report our initial data from this effort.