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2014 22nd International Conference on Very Large Scale Integration
2014 22nd International Conference on Very Large Scale Integration
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1.
Decimal engine for energy-efficient multicore processors
机译:
用于节能多核处理器的十进制引擎
作者:
Nannarelli Alberto
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
energy conservation;
floating point arithmetic;
multiprocessing systems;
system-on-chip;
accelerators;
binary floating-point division;
dark silicon era;
decimal engine;
decimal floating-point operations;
energy-efficient multicore processors;
hybrid BFP-DFP engine;
multicore system-on-chips;
square root;
Clocks;
Engines;
Hardware;
Program processors;
Registers;
Silicon;
2.
Low-power high-speed current mode logic using Tunnel-FETs
机译:
使用隧道FET的低功耗高速电流模式逻辑
作者:
Wei-Yu Tsai
;
Huichu Liu
;
Xueqing Li
;
Narayanan Vijaykrishnan
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
MOSFET;
current-mode logic;
low-power electronics;
tunnel transistors;
FinFET CML circuits;
bit rate 20 Gbit/s;
bit rate 50 Gbit/s;
buffer;
high-speed data transceivers;
low-power high-speed current mode logic;
low-voltage interface circuit design;
multiplexer;
on-off current ratio;
power consumption;
static logic;
steep subthreshold slope;
switching speed;
tunnel-FET;
tunneling-field-effect-transistor;
voltage-swing;
FinFETs;
Integrated circuit modeling;
Logic gates;
Power demand;
Silicon;
CML high-frequency;
TFET;
low-p;
3.
Multi-terminal PCB escape routing for digital microfluidic biochips using negotiated congestion
机译:
使用协商拥塞的数字微流控生物芯片的多端子PCB逃逸路由
作者:
McDaniel J.
;
Grissom Daniel
;
Brisk Philip
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
bioMEMS;
biological techniques;
lab-on-a-chip;
microfluidics;
network routing;
printed circuit design;
FPGA routing;
control pin;
digital microfluidic biochips;
maze routing;
multiple electrodes;
multiterminal PCB escape routing;
multiterminal escape routing solutions;
negotiated congestion;
pin-constrained DMFBs;
printed circuit board design;
single-terminal nets;
Algorithm design and analysis;
Arrays;
Benchmark testing;
Electrodes;
Pins;
Routing;
Wires;
4.
Realizing a security aware triple modular redundancy scheme for robust integrated circuits
机译:
为鲁棒集成电路实现安全意识的三重模块化冗余方案
作者:
Gunti Nagendra Babu
;
Khatri Aman
;
Lingasubramanian Karthikeyan
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
integrated circuit reliability;
integrated circuit testing;
logic testing;
probability;
redundancy;
security;
transient analysis;
IC malicious alteration;
PM;
TMR scheme;
Trojan detection;
confidential information leakage;
detection sensitivity;
hardware Trojan;
logic based testing;
probabilistic model;
probability distribution;
robust integrated circuit;
security aware reliability model;
security aware triple modular redundancy scheme;
side channel based testing;
third party IC manufacturer;
transient error;
triple m;
5.
Laser-induced fault effects in security-dedicated circuits
机译:
安全专用电路中激光引起的故障影响
作者:
Leveugle R.
;
Maistri P.
;
Vanhauwaert P.
;
Lu Feng
;
Di Natale G.
;
Flottes M.-L.
;
Rouzeyre B.
;
Papadimitriou A.
;
Hely D.
;
Beroulle V.
;
Hubert Guillaume
;
De Castro S.
;
Dutertre J.-M.
;
Sarafianos A.
;
Boher N.
;
Lisart M.
;
Damiens J.
;
Candelier P.
;
Tavernier C.
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
CAD;
lasers;
network synthesis;
silicon-on-insulator;
CAD tools;
FDSOI technology;
LIESSE project;
abstraction;
circuit technology;
counter-measures;
design flow;
error models;
fault models;
laser characteristics;
laser-induced fault effects;
physical effects;
security-dedicated circuits;
size 28 nm;
thwart laser-based attacks;
Analytical models;
Circuit faults;
Integrated circuit modeling;
Laser modes;
Measurement by laser beam;
Semiconductor lasers;
Solid modeling;
Counter-measures;
Fault attacks;
Fault models;
Hardware s;
6.
Improved read and write margins using a novel 8T-SRAM cell
机译:
使用新型8T-SRAM单元提高了读取和写入余量
作者:
Moradi Farshad
;
Madsen Jens K.
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
CMOS memory circuits;
SRAM chips;
low-power electronics;
6TSRAM cell;
TSMC CMOS technology;
improved read and write margins;
read static noise margin;
size 65 nm;
subthreshold 8T-SRAM cell;
total leakage power;
ultra-low power applications;
voltage 1 V;
Computer architecture;
Microprocessors;
Partial discharges;
SRAM cells;
Standards;
Transistors;
Low-Power;
SRAM;
Subthreshold;
Write Margin;
7.
Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI)
机译:
集成电路的电磁分析,解密和逆向工程(E-MATA HARI)
作者:
Chusseau Laurent
;
Omarouayache Rachid
;
Raoult Jeremy
;
Jarrix Sylvie
;
Maurine P.
;
Tobich Karim
;
Bover Alexandre
;
Vrignon Bertrand
;
Shepherd John
;
Thanh-Ha Le
;
Berthier Mael
;
Riviere Lionel
;
Robisson B.
;
Ribotta Anne-Lise
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
electromagnetic waves;
integrated circuit technology;
optimisation;
reverse engineering;
E-MATA HARI;
IC logic;
IC security;
beating countermeasures;
crypto codes;
electromagnetic analysis;
electromagnetic deciphering;
electromagnetic fault injections;
electromagnetic reverse engineering;
fault propagation;
integrated circuits;
near-field probe;
near-field setup;
physical optimization;
signal management;
Circuit faults;
Ferrites;
Probes;
Sensors;
System-on-chip;
Voltage measurement;
8.
Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation
机译:
背板/ FDA相关性-FDA取代商用背板进行SoC以太网电气验证
作者:
Mendoza-Bonilla Jesus-Andres
;
Cortez-Ibarra Alejandro
;
Vega-Ochoa Edgar-Andrei
;
Rangel-Patino Francisco
;
Gore Brandon
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
crosstalk;
electric connectors;
integrated circuit testing;
local area networks;
system-on-chip;
Ethernet post silicon validation;
FDA;
SoC Ethernet electrical validation;
TTM pressures;
attenuation specifications;
backplane environment connector characterization;
backplane-FDA correlation-FDA;
bit rate 2.5 Gbit/s;
commercial backplanes;
connector measurements;
crosstalk;
enhanced electrical validation testing methodology;
frequency dependent attenuator;
gigabit per second data rates;
high pin count;
high speed lin;
9.
AES design space exploration new line for scan attack resiliency
机译:
AES设计太空探索新系列以提高扫描攻击的弹性
作者:
Ali Sk Subidh
;
Sinanoglu Ozgur
;
Karri Ramesh
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
cryptography;
design for testability;
AES design space exploration;
DFT test infrastructure;
advanced encryption standard;
cryptochips;
design style;
input-output pairs;
normal mode;
response compaction;
round operation;
round register;
scan attack resiliency;
secret key;
side-channel attacks;
test mode;
word length 128 bit;
Ciphers;
Clocks;
Computer architecture;
Encryption;
Hamming distance;
Microprocessors;
Registers;
AES Scan Chain;
Scan Attack;
Scan-based DFT;
Security;
Testability;
10.
Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity
机译:
功耗对基于28nm FPGA的片上系统中子灵敏度的影响
作者:
Bruni G.
;
Rech P.
;
Tambara L.
;
Nazar G.L.
;
Kastensmidt F.L.
;
Reis R.
;
Paccagnell A.
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
field programmable gate arrays;
neutrons;
sensitivity analysis;
system-on-chip;
FPGA configuration memory cross section;
SoC;
embedded electronic device;
power dissipation effect;
radiation experiment;
silicon die temperature;
size 28 nm;
system on chip neutron sensitivity;
Field programmable gate arrays;
Heating;
Ocean temperature;
Power dissipation;
System-on-chip;
Temperature measurement;
Temperature sensors;
FPGa;
Power Dissipation;
Radiation Sensitivity;
System On Chips;
Temperature;
11.
A novel non-minimal turn model for highly adaptive routing in 2D NoCs
机译:
一种新颖的非最小转弯模型,用于二维NoC中的高度自适应路由
作者:
Kumar Manoj
;
Laxmi V.
;
Gaur M.S.
;
Daneshtalab Masoud
;
Zwolinski Mark
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
graph theory;
network routing;
network-on-chip;
2D NoC;
ACDG;
CMP;
MPSoC;
NoC;
acyclic channel dependency graph;
bus-based interconnects;
congestion-aware adaptive routing algorithm;
deadlock freedom;
extended channel dependency graph;
micro-architectures;
minimal routes;
network performance improvement;
network-on-chip;
noncongested regions;
nonminimal turn model;
routing turns;
traffic load;
Adaptation models;
Algorithm design and analysis;
Clocks;
Heuristic algorithms;
Routing;
System recovery;
Networks-on-Chip congest;
12.
Logic synthesis and verification on fixed topology
机译:
固定拓扑的逻辑综合与验证
作者:
Fujita Masayuki
;
Mishchenko Alexander
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
combinational circuits;
formal verification;
logic design;
logic testing;
network topology;
SAT;
combinational circuits;
fixed circuit topology;
formal verification;
logic synthesis;
logic verification;
minimum ECO;
net lists;
test vector generation method;
Adders;
Circuit topology;
Logic gates;
Radiation detectors;
Table lookup;
Topology;
Vectors;
13.
Reducing test time for 3D-ICs by improved utilization of test elevators
机译:
通过提高测试升降机的利用率来减少3D-IC的测试时间
作者:
Muthyala Sreenivaas S.
;
Touba Nur /A/.
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
data compression;
integrated circuit testing;
three-dimensional integrated circuits;
3D-ICs;
TAM;
TSVs;
compressed test data;
encoding efficiency;
free variables;
sequential linear decompressors;
serialized data;
test access mechanism;
test compression scheme;
test cubes;
test data serializer;
test elevator utilization;
test time reduction;
tester storage;
through-silicon-vias;
Bandwidth;
Clocks;
Computer architecture;
Elevators;
Encoding;
Frequency conversion;
Testing;
14.
Optimized active and power-down mode refresh control in 3D-DRAMs
机译:
优化的3D-DRAM中的活动和掉电模式刷新控制
作者:
Jung Moongon
;
Weis Christian
;
Wehn Norbert
;
Sadri Mohammadsadegh
;
Benini Luca
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
DRAM chips;
integrated circuit design;
integrated circuit modelling;
three-dimensional integrated circuits;
3D integration;
3D stacked systems;
3D structure;
3D-DRAMs;
DRAM cells;
DRAM controller model;
DRAM refresh power;
SystemC TLM-2.0;
bank-wise refresh;
energy reduction;
future density optimized mobile computing platforms;
lateral temperature variations;
optimized active mode refresh control;
per DRAM array hotspot detector;
power density;
power estimation;
power-down mode policy;
power-down mode refresh contro;
15.
VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplers
机译:
带有无乘数吉布斯采样器的基于MCMC的并行MIMO检测器的VLSI设计
作者:
Auras Dominik
;
Deidersen Uwe
;
Leupers Rainer
;
Ascheid Gerd
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
MIMO systems;
Markov processes;
Monte Carlo methods;
VLSI;
detector circuits;
AT-efficiency improvement;
MIMO max-log detection;
SNR regime;
VLSI design;
dynamic scaling;
multiantenna system;
multiple-input multiple-output system;
multiplier-free Gibbs sampler;
noise density;
parallel MCMC-based MIMO detector;
signal to noise ratio;
soft-input soft-output Markov chain Monte Carlo based MIMO detection;
stochastic detector;
very-large-scale integration;
Computer architecture;
Detectors;
MIMO;
Measurement;
Multiplexing;
R;
16.
A low power 720p motion estimation processor with 3D stacked memory
机译:
具有3D堆栈存储器的低功耗720p运动估计处理器
作者:
Shuping Zhang
;
Jinjia Zhou
;
Dajiang Zhou
;
Goto Satoshi
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
electronic design automation;
integrated circuit design;
low-power electronics;
memory architecture;
motion estimation;
storage management chips;
three-dimensional integrated circuits;
2D electronic design automation;
2D technology;
3D physical design;
3D stacked memory architecture;
3D stacking architecture;
EDA tools;
F2F pad;
IO pins;
MEP die;
TSV;
TSV-F2F placement;
core power consumption reduction;
data transmission;
face-to-face pad;
floor plan optimization;
low power 720p motion estimation processor;
memory con;
17.
Study of on-chip vias of resonant rotary traveling wave oscillators
机译:
谐振旋转行波振荡器的片上通孔的研究
作者:
Figueroa Javier Osorio
;
Linares Aranda Monico
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
integrated circuits;
oscillators;
transmission lines;
travelling wave tubes;
H trees;
IC;
RTWO;
X trees;
clock signal distribution networks;
closed loop;
integrated circuits;
mobius termination;
odd mode differential transmission lines;
on-chip vias;
operation frequencies;
parasitic elements;
physical shapes;
power consumption;
power consumption reduction;
resonant ring;
resonant rotary traveling wave oscillators;
resonant structures;
spine;
submicron technologies;
Clocks;
Metals;
Oscillators;
Power demand;
Registers;
Reson;
18.
Modeling, analysis and exploration of layers: A 3D computing architecture
机译:
图层建模,分析和探索:3D计算架构
作者:
Rakossy Zoltan Endre
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
circuit simulation;
energy conservation;
functional programming;
high level synthesis;
integrated circuit design;
integrated circuit modelling;
integrated circuit testing;
reconfigurable architectures;
three-dimensional integrated circuits;
3D computing architecture;
3D silicon technology;
3D structure;
application mapping flow;
functional programming theory;
functional reconfiguration theoretical concepts;
high energy efficiency;
high-level design methodology;
layered reconfigurable architecture;
memory bandwidt;
19.
Advances on the state of the art in QDI design
机译:
QDI设计的最新进展
作者:
Moreira Matheus T.
;
Calazans Ney L. V.
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
asynchronous circuits;
logic design;
QDI circuit design;
aggressive process variations;
asynchronous circuits;
battery-based applications;
cell library design;
cell-based approaches;
circuit synthesis;
clock power;
complex systems;
contemporary chip;
global clock signal distribution;
power budgets;
quasidelay-insensitive;
synchronous chip total power;
synchronous paradigm capability;
transistors;
Asynchronous circuits;
Context;
Layout;
Libraries;
Logic gates;
Topology;
20.
Simulated annealing-based placement for microfluidic large scale integration (mLSI) chips
机译:
用于微流大规模集成(mLSI)芯片的基于模拟退火的放置
作者:
McDaniel J.
;
Parker Brendon
;
Brisk Philip
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
circuit optimisation;
integrated circuit design;
large scale integration;
microfluidics;
microvalves;
simulated annealing;
channel distance;
chemically inert elastomeric substrate;
design automation enhancement;
directed initial placement;
flow channel intersections;
grid representation;
heterogeneous component sizes;
mLSI;
microfluidic large scale integration chips;
microvalves;
objective function;
perturbation operations;
random placement;
routability;
simulated annealing-based placement;
spacing rules;
Fluids;
Line;
21.
Silicon photonics design rule checking: Application of a programmable modeling engine for non-Manhattan geometry verification
机译:
硅光子学设计规则检查:可编程建模引擎在非曼哈顿几何图形验证中的应用
作者:
Ruping Cao
;
Ferguson John
;
Gays Fabien
;
Drissi Youssef
;
Arriordaz Alexandre
;
OConnor Ian
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
elemental semiconductors;
integrated circuit layout;
integrated optics;
silicon;
PIC;
Si;
layout annotation;
mathematical expressions;
multidimensional rule checking;
nonManhattan geometry verification;
photonic integrated circuit physical designs;
programmable modeling engine;
silicon photonics DRC technique;
silicon photonics design rule checking;
Debugging;
Fabrication;
Geometry;
Layout;
Shape;
Silicon photonics;
22.
A quantum algorithm processor architecture based on register reordering
机译:
基于寄存器重排序的量子算法处理器架构
作者:
Nakanishi Masaki
;
Matsuyama Miki
;
Yokoo Yumi
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
field programmable gate arrays;
microprocessor chips;
parallel architectures;
quantum computing;
FPGA;
clock frequency;
large multiplexers;
parallel computation;
probability amplitudes;
quantum algorithm processor architecture;
quantum bits;
quantum computation;
quantum computer simulators;
register reordering method;
software simulators;
target basis states;
Arrays;
Computers;
Logic gates;
Quantum computing;
Registers;
Vectors;
23.
Complementary logic interface for high performan optical computing with OLUT
机译:
互补逻辑接口,用于使用OLUT进行高性能光学计算
作者:
Zhen Li
;
Le Beux Sebastien
;
OConnor Ian
;
Monat Christelle
;
Letartre Xavier
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
Boolean functions;
energy conservation;
logic circuits;
optical logic;
parallel architectures;
table lookup;
OLUT size;
area overhead;
complementary Boolean logic functions;
complementary logic interface;
energy-efficient logic architecture;
energy-efficient photonic reconfigurable computing;
hardware-efficient photonic reconfigurable computing;
high performance optical computing;
look up table;
on-chip optical FPGAs;
optical LUT;
optical laser power worst-case evaluation;
optical power;
parallel logic architectur;
24.
Towards energy effective LDPC decoding by exploiting channel noise variability
机译:
利用信道噪声可变性实现节能LDPC解码
作者:
Marconi Thomas
;
Spagnol Christian
;
Popovici Emanuel
;
Cotofana Sorin
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
circuit noise;
decoding;
energy consumption;
field programmable gate arrays;
parity check codes;
quality of service;
DVS;
QoS requirement;
Virtex-6 FPGA;
channel noise variability;
channel quality variation;
communication system;
decoder performance;
degradation stochastic resonance;
energy consumption;
energy effective LDPC decoding;
energy reduction method;
field programable array;
low-density parity-check code;
optimal tradeoff;
parallel LDPC decoder;
power consumption;
quality of service;
Bit error rate;
Decoding;
F;
25.
Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip
机译:
基于硅的3D网格片上网络的穿通孔布局和映射策略
作者:
Manna Kanchan
;
Chattopadhyay Subrata
;
Sengupta Indranil
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
integrated circuit design;
network-on-chip;
three-dimensional integrated circuits;
3D mapping;
3D mesh based network-on-chip;
NoC design;
TSV geometry;
three-dimensional network-on-chip design;
through silicon via mapping strategy;
through silicon via placement strategy;
Bandwidth;
Benchmark testing;
Network-on-chip;
Routing;
Three-dimensional displays;
Through-silicon vias;
Topology;
26.
Electromagnetic analysis and fault injection onto secure circuits
机译:
电磁分析和故障注入安全电路
作者:
Maistri P.
;
Leveugle R.
;
Bossuet L.
;
Aubert A.
;
Fischer V.
;
Robisson B.
;
Moro N.
;
Maurine P.
;
Dutertre J.-M.
;
Lisart M.
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
cryptography;
electromagnetic compatibility;
fault diagnosis;
network analysis;
EM emissions;
active attack technique;
electromagnetic analysis;
electromagnetic emissions;
fault injection tool;
hardware cryptography;
implementation attacks;
secure circuits;
Circuit faults;
Clocks;
Cryptography;
Electromagnetics;
Generators;
Harmonic analysis;
Probes;
EM;
Fault Attacks;
Secure implementations;
Side Channel Analysis;
27.
Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability
机译:
Verilog / SPICE混合模型的仿真框架:使用HLA / RTI实现模型可重用性的Verilog和SPICE模拟器的互操作
作者:
Moon Gi Seok
;
Dae Jin Park
;
Geun Rae Cho
;
Tag Gon Kim
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
SPICE;
circuit simulation;
hardware description languages;
integrated circuit design;
mixed analogue-digital integrated circuits;
synchronisation;
HLA-RTI;
IEEE-std HLA interface;
IEEE-std Verilog procedural interface;
RTI;
SPICE circuit netlist;
SPICE procedural interface;
SPICE simulators;
Verilog simulators;
Verilog-SPICE mixed model;
adapters;
analog circuits;
analog-digital signals;
component interface;
digitally controlled buck converter simulation;
high level architecture;
legacy digital blocks;
mixed legacy V;
28.
Detailed placement accounting for technology constraints
机译:
详细的布局考虑了技术限制
作者:
Kennings Andrew
;
Darav Nima Karimpour
;
Behjat Laleh
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
circuit layout;
circuit optimisation;
network routing;
ISPD2014 placement contest;
cell alignment;
cell placement;
circuit placement;
detailed placement accounting;
global placement;
optimization sequence;
pin access problem;
pin short;
rough placement;
routability issue;
spacing requirement;
technology constraint;
Benchmark testing;
Dynamic programming;
Heuristic algorithms;
Metals;
Pins;
Routing;
Wires;
29.
Circuit to reduce Gate Induced Drain Leakage in CMOS output buffers
机译:
减少CMOS输出缓冲器中栅极感应的漏极泄漏的电路
作者:
Ravi Hari Anand
;
Goel Mayank
;
Bhilawadi Prasad
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
CMOS integrated circuits;
buffer circuits;
CMOS output buffers;
GIDL current reduction;
gate induced drain leakage reduction;
CMOS integrated circuits;
Computer architecture;
Generators;
Logic gates;
MOS devices;
Microprocessors;
Transistors;
CMOS output buffer;
GIDL;
IO;
low power;
30.
Deconvolution algorithm dependencies of estimation errors of RTN effects on subnano-scaled SRAM margin variation
机译:
反卷积算法对RTN影响的估计误差对亚纳米级SRAM容限变化的依赖性
作者:
Yamauchi Hiroyuki
;
Somha Worawit
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
SRAM chips;
deconvolution;
gradient methods;
maximum likelihood estimation;
MATLAB;
RDF;
RTN effects;
deconvolution algorithm dependencies;
estimation errors;
fail-bit-count error;
maximum-likelihood gradient sequence;
random dopant fluctuation;
random telegraph noise;
subnanoscaled SRAM margin variation;
Convolution;
Deconvolution;
MATLAB;
Noise;
Probability density function;
Random access memory;
Resource description framework;
Deconvolution;
MATLAB-deconvolution function;
Random telegraph noise;
SRAM margin variatio;
31.
Soft error effects analysis and mitigation in VLIW safety-critical applications
机译:
VLIW安全关键型应用程序中的软错误影响分析和缓解
作者:
Sabena D.
;
Reorda M. Sonza
;
Sterpone L.
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
embedded systems;
fault tolerance;
integrated circuit reliability;
microprocessor chips;
parallel architectures;
power consumption;
radiation hardening (electronics);
redundancy;
safety;
C code level;
TMR-based software technique;
VLIW architectures;
VLIW processor reliability;
VLIW safety-critical applications;
cross-domain error reduction;
embedded processing systems;
embedded signal applications;
fault coverage;
fault tolerance;
high computational performances;
nanoscale technology;
power consumption;
reduced cloc;
32.
A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow
机译:
用于嵌入式系统自动TLM到RTL转换的工具,以实现无缝验证流程
作者:
Bel Hadj Amor Zeineb
;
Pierre Laurence
;
Borrione Dominique
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
embedded systems;
integrated circuit design;
software engineering;
system-on-chip;
ABV;
SoCs;
SystemC TLM;
abstraction level;
assertion-based verification flow;
automatic TLM-to-RTL conversion;
complex systems on chips;
design flow;
embedded systems;
hardware block verification;
hardware component assembling;
register transfer level;
seamless verification flow;
software component assembling;
software development;
system level property;
transaction level modeling;
transformation rules;
virtual prototypes;
Clocks;
Hardwa;
33.
Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs
机译:
用于ΣΔADC的动态测试的数字三元激励评估
作者:
Dubois Matthieu
;
Stratigopoulos Haralampos-G
;
Mir Salvador
;
Barragan Manuel J.
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
circuit testing;
dynamic testing;
embedded systems;
sigma-delta modulation;
ΣΔ ADCs;
advanced simulation framework;
behavioural simulations;
digital bitstream stimulus;
digital ternary stimuli evaluation;
digital test technique;
dynamic test;
electrical simulations;
embedded test technique;
high-volume manufacturing;
standard high-resolution analog sine-wave stimulus;
statistical tools;
test escape metrics;
transistor-level simulations;
yield loss;
Computational modeling;
Discrete Fourier transforms;
Modulation;
Mont;
34.
Dynamic programming-based lifetime aware adaptive routing algorithm for Network-on-Chip
机译:
片上网络基于动态编程的寿命感知自适应路由算法
作者:
Liang Wang
;
Xiaohang Wang
;
Mak Terrence
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
dynamic programming;
integrated circuit reliability;
network routing;
network-on-chip;
MTTF;
NoC;
NoP routing;
XY routing;
dynamic programming;
lifetime aware adaptive routing algorithm;
lifetime budget metric;
network-on-chip;
oddeven routing;
reliability issue;
router lifetime reliability;
technology scaling;
workload;
Benchmark testing;
Dynamic programming;
Heuristic algorithms;
Mathematical model;
Reliability;
Routing;
Runtime;
35.
A common architecture for co-simulation of SystemC models in QEMU and OVP virtual platforms
机译:
在QEMU和OVP虚拟平台中共同仿真SystemC模型的通用架构
作者:
Cucchetto Filippo
;
Lonardi Alessandro
;
Pravadelli Graziano
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
application program interfaces;
virtual prototyping;
OVP virtual platforms;
QEMU platforms;
SystemC designs;
TLM 2.0 wrappers;
common cosimulation approach;
cycle-accurate models;
open virtual platform;
opportune API;
virtual prototyping;
Bridges;
Computer architecture;
Hardware;
Operating systems;
Time-varying systems;
Virtual prototyping;
36.
Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor
机译:
快速准确评估流水线微处理器中的寄存器寿命和临界度
作者:
Chibani K.
;
Ben-Jrad M.
;
Portolan M.
;
Leveugle R.
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
fault tolerant computing;
multiprocessing systems;
pipeline processing;
application failures;
data dependencies;
fast-forwarding connections;
fault injections;
internal registers;
micro-architecture features;
pipelined microprocessor;
register criticality;
register lifetime;
soft errors;
software optimizations;
Computational modeling;
Microprocessors;
Pipelines;
Prediction algorithms;
Program processors;
Registers;
dependability soft errors;
lifetime;
microprocessor;
pipeline;
register criticality;
37.
Reconfigurable forward homography estimation system for real-time applications
机译:
用于实时应用的可重构正向单应性估计系统
作者:
Popovic Vladan
;
Leblebici Yusuf
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
computer vision;
data compression;
field programmable gate arrays;
inverse problems;
table lookup;
FPGA implementation;
computer vision algorithm;
homography calculation;
homography error;
image frame;
image processing algorithm;
image quality;
inverse problem;
look-up table based systems;
memory requirement reduction;
peak signal-to-noise-ratio;
real-time applications;
reconfigurable forward homography estimation system;
Cameras;
Estimation;
Field programmable gate arrays;
Image resolution;
Real-time systems;
Registe;
38.
Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors
机译:
通过重新排列旋转因子来实现高效节能的多核FFT数据路径
作者:
Ghissoni Sidinei
;
da Costa Eduardo /A/. C.
;
Goncalves da Luz Angelo
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
digital arithmetic;
energy conservation;
fast Fourier transforms;
multiprocessing systems;
power aware computing;
power consumption;
SYNOPSYS design compiler;
XFAB technology;
improved Anedma heuristic-based algorithm;
input data multiplications;
power consumption minimization;
power efficient multicore FFT datapaths;
power reduction;
size 180 nm;
switching activity;
twiddle factors;
Algorithm design and analysis;
Hamming distance;
Heuristic algorithms;
Multicore processing;
Partitioning algorithms;
Power demand;
heu;
39.
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study
机译:
交叉Nos中虚拟通道流控制的交叉开关复制与共享:一项比较研究
作者:
Miorandi Gabriele
;
Ghiribaldi Alberto
;
Nowick Steven M.
;
Bertozzi Davide
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
asynchronous circuits;
network-on-chip;
VC flow control;
asynchronous NoC;
asynchronous networks;
complex control circuits;
control logic;
crossbar replication;
design complexity;
design space exploration;
multistage switch allocation;
on-chip interconnection networks;
performance optimization techniques;
resource replication;
transition-signalling bundled-data;
virtual channel flow control;
Ports (Computers);
Protocols;
Resource management;
Routing;
Sensors;
Switches;
40.
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation
机译:
可扩展且高效节能的可重构加速器,用于按列旋转给定
作者:
Rakossy Zoltan Endre
;
Merchant Farhad
;
Acosta-Aponte Axel
;
Nandy S.K.
;
Chattopadhyay Abhiroop
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
energy conservation;
parallel algorithms;
parallel architectures;
power aware computing;
reconfigurable architectures;
column-wise Givens rotation;
division free Givens rotation algorithms;
efficient mapping strategy;
energy-efficient reconfigurable accelerator;
layered reconfigurable architecture;
memory bandwidth;
multiple element annihilation;
parallel algorithms;
scalable reconfigurable accelerator;
square root;
Algorithm design and analysis;
Arrays;
Bandwidth;
Kernel;
Registers;
Scalability;
3D Architecture;
ADL;
41.
Inference of channel types in micro-architectural models of on-chip communication networks
机译:
片上通信网络微体系结构模型中的信道类型推断
作者:
van Gastel Bernard
;
Verbeek Freek
;
Schmaltz Julien
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
integrated circuit modelling;
multiprocessing systems;
network-on-chip;
telecommunication channels;
telecommunication networks;
STMicroelectronics;
communication channel;
deadlock detection;
formal analysis;
inductive invariants;
microarchitectural models;
multicore era;
multiprocessor system-on-chips;
network-on-chips;
on-chip communication networks;
symbolic channel type inference;
xMAS language;
Algorithm design and analysis;
Color;
Computational modeling;
Data structures;
Inference algorithms;
Payloads;
Switches;
42.
Self similarity and interval arithmetic based leakage optimization in RTL datapaths
机译:
RTL数据路径中基于自相似度和区间算法的泄漏优化
作者:
Pendyala Shilpa
;
Katkoori Srinivas
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
Monte Carlo methods;
adders;
digital arithmetic;
fractals;
simulated annealing;
DSP filters;
Monte Carlo simulation;
RTL datapaths;
adder modules;
data path intensive circuits;
empirical observations;
interval arithmetic;
leakage distribution;
leakage optimization;
low leakage input vector determination;
multiplier modules;
self similarity;
simulated annealing;
size 16 nm;
top down interval propagation technique;
Adders;
Fractals;
Integrated circuit modeling;
Mathematical model;
Monte Carlo methods;
Simulated annealing;
43.
Automated functional coverage directed for complex digital systems
机译:
针对复杂数字系统的自动功能覆盖
作者:
Martinez Cruz Alfonso
;
Barron Fernandez Ricardo
;
Molina Lozano Heron
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
network synthesis;
DUV full behavior;
automated functional coverage;
complex digital systems;
coverage points;
device under verification full behavior;
hybrid methods;
reduced metaheuristic versions;
test points;
test sequences;
vector sequences;
Binary Differential Evolution algorithm;
Binary Particle SwarmOptimization algorithm;
Coverage Points;
Directed Functional Verification;
functional verification;
44.
Energy-efficient partitioning of hybrid caches in multi-core architecture
机译:
多核架构中混合缓存的节能分区
作者:
Dongwoo Lee
;
Kiyoung Choi
会议名称:
《2014 22nd International Conference on Very Large Scale Integration》
|
2014年
关键词:
SRAM chips;
cache storage;
energy consumption;
multiprocessing systems;
SRAM cache;
STT-RAM cache;
block fill;
cache block;
energy consumption reduction;
energy-efficient partitioning;
multicore architecture;
read-write aware region-based hybrid cache architecture;
spin-transfer torque RAM;
Benchmark testing;
Energy consumption;
Magnetic tunneling;
Multicore processing;
Random access memory;
Torque;
Spin-Transfer Torque RAM (STT-RAM);
cache partitioning;
hybrid caches;
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