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A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock

机译:通过控制时钟,低功耗定时差错电路

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Timing error is now getting increased attention due to the high rate of error-occurrence on semiconductors. Even slight external disturbance can threaten the timing margin between successive clocks since the latest semiconductor operates with high frequency and small supply voltage. To deal with a timing error, many techniques have been introduced. Nevertheless, existing methods that mitigate a timing error mostly have time-delaying mechanisms and too complex operation, resulting in a timing problem on clock-based systems and hardware overhead. In this article, we propose a novel timing-error-tolerant method that can correct a timing error instantly through a simple mechanism. By modifying a clock in a flip-flop, the proposed system can recover a timing error without the loss of time in the clock-based system. Furthermore, due to the compact mechanism, the proposed system has low hardware overhead in comparison with existing timing-error-tolerant systems that can recover the error instantly. To verify our method, the proposed circuit was extensively simulated by addressing PVT variations. Moreover, it was implemented in several benchmark designs, including a microprocessor.
机译:定时错误现在由于半导体上的误差率高而受到提高。即使是略微的外部干扰也会威胁到连续时钟之间的时序幅度,因为最新的半导体以高频和小电源电压运行。要处理定时错误,已经介绍了许多技术。尽管如此,减轻定时误差主要具有时间延迟机制的现有方法和运行过于复杂,导致基于时钟的系统和硬件开销的定时问题。在本文中,我们提出了一种新颖的定时差错方法,可以通过简单的机制立即纠正定时错误。通过修改触发器中的时钟,所提出的系统可以在基于时钟的系统中丢失时间的情况下恢复定时误差。此外,由于机制紧凑,所提出的系统具有低硬件开销,与现有的定时差错系统相比,可以立即恢复错误。为了验证我们的方法,通过寻址PVT变型来广泛模拟所提出的电路。此外,它在包括微处理器的几个基准设计中实现。

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