A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits

摘要

This work presents a phase-locked loop (PLL)-based clock and data recovery (CDR) circuit with a lock detector loop to reduce the voltage ripple of voltage-controlled oscillator (VCO). A tunable charge pump is used in this work to adjust the charge current depending on the state of lock detector loop, which is determined by seven clocks with equal phase difference. An experimental prototype is implemented using a typical 0.18-m CMOS process to justify the performance. The measurement results reveal that lock detector loop could reduce the voltage amplitude of Vctrl, which is the control of VCO. Notably, the voltage amplitude of Vctrl is reduced 75% from 1 V to 250 mV.