PHASE LOCKED LOOP OPERATED BY ON-CHIP REFERENCE CLOCK, CLOCK DATA RECOVERY CIRCUIT, AND DATA RECEIVING APPARATUS

摘要

The present invention provides a phase locked loop for recovering a clock from a data signal. The phase locked loop comprises: an on-chip oscillator to generate a reference clock; a frequency comparator to count a clock of a data signal received during one clock of the reference clock to output a data signal count value; a programmable divider to demultiply a recovery clock at a demultiplying rate determined by the data signal count value to output a demultiplied clock; a phase-frequency detector to detect a phase difference between the reference clock and the demultiplied clock; a charge pump/LPF to convert the phase difference detected by the phase-frequency detector into a control voltage; and a voltage control oscillator to output the recovery clock by the control voltage.;COPYRIGHT KIPO 2016