Multi-phase multiplying delaylocked loop based digital clock data recovery apparatus and method for recovery clock data

摘要

The present invention relates to an apparatus and method for recovering digital clock data based on a multi-phase multiplying delay locked loop, comprising: a digital clock data recovery circuit for receiving data output from a receiver and generating recovered data and a recovered clock; and a multi-phase multiplying delay lock loop that receives a reference clock, performs clock frequency multiplication and phase locking with the reference clock, and outputs a multi-phase reference clock of the digital clock data recovery circuit. A delay locked loop-based digital clock data recovery apparatus and method are provided.