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Crosstalk noise reduction in synthesized digital logic circuits

机译:合成数字逻辑电路的串扰降噪

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As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: First, it can destroy logical information carried by a circuit net. Second, it causes delay uncertainty: Non critical paths might become critical because of noise. As a result, circuit speed becomes limited by noise, primarily because of capacitive coupling between wires. Most design approaches address the crosstalk noise problem at the layout generation stage, or via postlayout corrections. With continued scaling, too many circuit nets require corrections for noise, causing a design convergence problem. This work suggests to consider noise at the gate-level netlist generation stage. The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. A design flow is proposed for automatically synthesizing CMOS circuits that have improved robustness to noise effects, using standard tools, by limiting the range of gate strengths available in the cell library. The synthesized circuits incur a penalty in area/power, which can be partially recovered in a single postlayout corrective iteration. Results of design experiments indicate that delay uncertainty is the most important noise-related concern in synthesized static CMOS logic. Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. By using the proposed design flow, timing uncertainty was reduced to below 3%, with area and power penalties below 20%.
机译:随着CMOS技术缩放到深层潜伏型状态,数字噪声正在成为与区域,时序和电源相当的重要性的公制,用于分析和设计CMOS VLSI系统。噪音在数字电路中有两个有害影响:首先,它可以破坏电路网承载的逻辑信息。其次,它导致延迟不确定性:由于噪音,非关键路径可能变得危急。结果,电路速度受到噪声的限制,主要是因为电线之间的电容耦合。大多数设计方法在布局生成阶段或通过后结校正来解决串扰噪声问题。随着持续的缩放,太多电路网需要校正噪声,导致设计融合问题。这项工作表明,在门级网表生成阶段考虑噪音。本文提出了对片上串扰模型的简化分析,并展示了合成电路块内局部电线之间的串扰的重要性。提出了一种设计流程,用于自动合成CMOS电路,通过限制单元库中可用的栅极强度的范围,利用标准工具改善了对噪声效果的稳健性的鲁棒性。合成电路在面积/功率中产生罚款,可以在单一后结算纠正迭代中部分恢复。设计实验结果表明,延迟不确定性是合成静态CMOS逻辑中最重要的噪声相关问题。使用标准合成方法,在微处理器电路的功能块中,已经观察到临界路径延迟差的差异高达时钟周期时间的18%。通过使用所提出的设计流程,时序不确定性降至3%以下,面积和功率罚款低于20%。

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