Simultaneous driver and wire sizing for performance and poweroptimization

摘要

In this paper, we study the simultaneous driver and wire sizingn(SDWS) problem under two objective functions: i) delay minimizationnonly, or ii) combined delay and power dissipation minimization. Wenpresent general formulations of the SDWS problem under these twonobjectives based on the distributed Elmore delay model withnconsideration of both capacitive power dissipation and short-circuitnpower dissipation. We show several interesting properties of the optimalnSDWS solutions under the two objectives, including an important resultnwhich reveals the relationship between driver sizing and optimal wirensizing. These results lead to polynomial time algorithms for computingnthe lower and upper bounds of optimal SDWS solutions under the twonobjectives, and efficient algorithms for computing optimal SDWSnsolutions under the two objectives. We have implemented these algorithmsnand compared them with existing design methods for driver sizing only ornindependent driver and wire sizing. Accurate SPICE simulation shows thatnour methods reduce the delay by up to 12%-49% and power dissipation byn26%-63% compared with existing design methods