Design and realization of high-performance wave-pipelined 8×8b multiplier in CMOS technology

摘要

Wave pipelining is a design technique for increasing thenthroughput of a digital circuit or system without introducing pipeliningnregisters between adjacent combinational logic blocks in thencircuit/system. However, this requires balancing of the delays along allnthe paths from the input to the output which comes the way of itsnimplementation. Static CMOS is inherently susceptible to delay variationnwith input data, and hence, receives a low priority for wave pipelinedndigital design. On the other hand, ECL and CML, which are amenable tonwave pipelining, lack the compactness and low power attributes of CMOS.nIn this paper we attempt to exploit wave pipelining in CMOS technology.nWe use a single generic building block in Normal Process ComplementarynPass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delaynalong all the propagation paths in the logic structure. An 8×8 bnmultiplier is designed using this logic in a 0.8 Μm technology. Thencarry-save multiplier architecture is modified suitably to support wavenpipelining, viz., the logic depth of all the paths are made identical.nThe 1 mm×0.6 mm multiplier core supports a throughput of 400 MHznand dissipates a total power of 0.6 W. We develop simple enhancements tonthe NPCPL building blocks that allow the multiplier to sustainnthroughputs in excess of 600 MHz. The methodology can be extended tonintroduce wave pipelining in other circuits as well