Built-in self-test (BIST) design of high-speed carry-free dividers

摘要

This paper presents the built-in self-test (BIST) design of anC-testable high-speed carry-free divider which can be fully tested by 72ntest patterns irrespective of the divider size. Using a graph labelingnscheme, the test patterns, expected outputs, and control signals can benrepresented by sets of labels and generated by a simple circuitry. As anresult, test patterns can be easily generated inside chips, responses tontest patterns need not to be stored, and use of expensive test equipmentnis not necessary. Results show that the hardware cost for generatingnsuch labels is virtually constant irrespective of the circuit size. Fornthe BIST design of a 64 b C-testable divider, its hardware overhead isnless than 5%