This paper presents the built-in self-test (BIST) design of a C-testable high-speed carry-free divider which can be fully tested by 72 test patterns irrespective of the divider size. Using a graph labeling scheme, the test patterns, expected outputs, and control signals can be represented by sets of labels and generated by a simple circuitry. As a result, test patterns can be easily generated inside chips, responses to test patterns need not to be stored, and use of expensive test equipment is not necessary. Results show that the hardware cost for generating such labels is virtually constant irrespective of the circuit size. For the BIST design of a 64 b C-testable divider, its hardware overhead is less than 5%.
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机译：本文介绍了一种可通过C测试的高速无载分频器的内置自检（BIST）设计，无论分频器的大小如何，它都可以通过72种测试模式进行全面测试。使用图形标记方案，测试模式，预期输出和控制信号可以由标记集表示并由简单的电路生成。结果，可以容易地在芯片内部生成测试图案，不需要存储对测试图案的响应，并且不需要使用昂贵的测试设备。结果表明，生成这种标签的硬件成本实际上是恒定的，与电路大小无关。对于64 b C可测试分频器的BIST设计，其硬件开销小于5％。
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