Instruction buffering to reduce power in processors for signalprocessing

摘要

Power consumption analyzes of embedded processors indicate that ansignificant amount of power is consumed in accessing memory and in thencontrol path. Based on this, and on the runtime characteristics ofnsignal processing applications, we advocate the use of instructionnbuffering as a power-saving technique for processors for signalnprocessing and multimedia applications. Two approaches, a decodedninstruction buffer (DIB) and a decoded instruction cache, arenconsidered. Performance improvements in representative applications innspeech processing such as, the vector sum excited linear predictionn(VSELP), linear prediction coding coefficient computation (LPC), andntwo-dimensional 2-D 8×8 DCT which is used in image compression,nare provided. The reduction in power obtained is between between 25 andn30%