提出了用于VLIW DSP处理器的硬件循环缓冲器的设计.该DSP处理器在结构上利用了在信号处理程序中循环经常出现这一特点,专门设计了硬件循环处理模块用来消除因循环跳转造成的流水线等待,以达到循环的零开销处理从而提高DSP的性能.设计过程中为了减小硬件开销,对循环的长度特点进行了分析,把循环分类两类并用不同的方法处理.结果表明循环跳转的处理是在独立模块中操作,没有造成流水线的等待提高了性能,该硬件循环的面积是3.8 k逻辑门.%An architecture and design of hardware loop buffer for a VLIW DSP is provided. Due to the characteristic of frequent repetitions of a few fixed algorithms in the DSP program, a special hardware module for handling the repetition is designed to eliminate the stall of pipeline caused by fetching the loop instructions in this DSP architecture. And the DSP performance is improved since the loop is handled with zero over-head. In order to minimize the hardware overhead, the repetitions are divided into two kinds according to the length of them and handled discriminatingly. The result shows that the jump of loop is operated in a separate module without stall of pipeline and thus the performance is improved. The area of the hardware loop buffer is 3.8 k logic gates.
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