LVDCSL: a high fan-in, high-performance, low-voltage differentialcurrent switch logic family

摘要

This paper presents a low voltage differential current switchnlogic (LVDCSL) gate capable of achieving high performance for largenfan-in gates. High fan-in is enabled by using a large heightnpredischarged N-channel metal-oxide-semiconductor (NMOS) trees. Thenpower penalty of an increased number of internal nodes in the gate isnmitigated by restricting their voltage swings. The salient features ofnthis low-voltage DCSL family are high speed for high fan-in large stacknheight NMOS trees, low power due to restricted internal voltage swings,nsimple interface to static complementary metal-oxide-semiconductorn(CMOS), and a latching nature which locks out inputs once outputs arenevaluated. Results show that LVDCSL is capable of working at under 2 Vnin a 0.35% CMOS process while being faster than comparable Domino gates.nAt the same time total power consumption is reduced. LVDCSL achieves 40%ndelay improvement and 22% power reduction in comparison with dual railnDomino gates for 8 bit carry look-ahead circuits. Results for thencritical path of an adder reveal that the complexity afforded by thengate, effectively decreases the number of logic levels and leads tonimproved performance