Single-Phase SP-Domino: A Limited-Switching Dynamic Circuit Technique for Low-Power Wide Fan-in Logic Gates

摘要

The high switching activity of wide fan-in dynamic domino gates introduces significant power overhead that poses a limitation on using these compact high-speed circuits. This paper presents a new limited-switching clock-delayed dynamic circuit technique, called SP-Domino, which achieves static-like switching behavior, while maintaining the low-area and high-performance characteristics of wide fan-in dynamic gates. SP-Domino is a single-phase footless domino that can be freely mixed with static gates and can provide inverting and non-inverting functions. Simulations on 8 and 16 inputs or gates show that SP-Domino reduces dynamic power by up to 63% compared to same-UNG and same-delay standard footless domino, and up to 56.9% compared to low-contention high-speed standard footless domino.