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Low-power, compact digital logic topology that facilitates large fan-in and high-speed circuit performance
Low-power, compact digital logic topology that facilitates large fan-in and high-speed circuit performance
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机译:低功耗,紧凑的数字逻辑拓扑,有助于实现大扇入和高速电路性能
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摘要
A circuit topology for implementing combinational logic functions with large fan-in, high speed, and low power consumption using a combination of dynamic and static gates. The circuit topology includes a dynamic gate and a Pseudo-NMOS gate coupled to the dynamic gate.
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