VLSI considerations for TESH: a new hierarchical interconnectionnetwork for 3-D integration

摘要

This paper discusses very large scale integration (VLSI) issues,nincluding reconfiguration and yield, for a new interconnection network,n“Tori connected mESHes (TESH)”. Its key features are thenfollowing: (1) it is hierarchical, thus allowing exploitation ofncomputation locality as well as easy expansion up to a millionnprocessors, (2) it permits efficient VLSI/ULSI (ultralarge scalenintegration) realization, and (3) it appears to be well suited fornthree-dimensional (3-D) implementation. This is due in part to the factnthat it requires far fewer number of vertical wires than most othernmulticomputer networks of comparable diameter, as demonstrated by a 4096nnode example. Presented in the paper are the architecture of the newnnetwork, node addressing and message routing, VLSI considerations, andnmost importantly, the reconfiguration and yield studies