Process Considerations in Restructurable VLSI (Very Large Scale Integration) for Wafer-Scale Integration

摘要

Wafer-scale integration has recently been demonstrated using a technique called Restructable VLSI. An array of logic cells embedded in programmable interconnect is fabricated in the wafer. All the parts are tested by wafer probing, and links are made or broken with a laser to wire the complete system. One such chip, a digital integrator 24 sq cm in area with 25 MHz input data rate, has been successfully programmed. This paper will describe the RVLSI concept and discuss several aspects of wafer fabrication which are unusual in this technology.