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The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance*

机译：VLsI互连电容的分层h自适应三维边界元计算*

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J Insong Hou; Zeyi Wang; Xianlong Hong;
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1. ParAFEMCap: A Parallel Adaptive Finite-Element Method for 3-D VLSI Interconnect Capacitance Extraction [J] . Chen G., Zhu H., Cui T., Microwave Theory and Techniques, IEEE Transactions on . 2012,第2期

机译：ParAFEMCap：3-D VLSI互连电容提取的并行自适应有限元方法
2. Comments on “ParAFEMCap: A Parallel Adaptive Finite-Element Method for 3-D VLSI Interconnect Capacitance Extraction” [J] . Ozgun O. Microwave Theory and Techniques, IEEE Transactions on . 2012,第6期

机译：关于“ ParAFEMCap：3-D VLSI互连电容提取的并行自适应有限元方法”的评论
3. Finite-Element Computation of Sensitivities of Interconnect Parasitic Capacitances to the Process Variation in VLSI [J] . Qu H., Kong L., Xu Y., IEEE Transactions on Magnetics . 2008,第6期

机译：互连寄生电容灵敏度对VLSI中工艺变化的有限元计算
4. The hierarchical h-adaptive 3-D boundary element computation of VLSI interconnect capacitance [C] . Jinsong Hou, Zeyi Wang . 1999

机译：VLSI互连电容的分层h自适应3-D边界元计算
5. Test generation for capacitance and inductance induced noise on interconnects in VLSI logic [D] . Sinha, Arani. 2006

机译：在VLSI逻辑中测试互连上电容和电感引起的噪声的测试
6. Interface and permittivity simultaneous reconstruction in electrical capacitance tomography based on boundary and finite-elements coupling method [O] . Shangjie Ren, Feng Dong -1

机译：基于边界和有限元耦合方法的电容层析成像界面和介电常数同时重建
7. BBE: Hierarchical Computation of 3-D Interconnect Capacitance with BEM Block Extraction ∗ [O] . Taotao Lu, Zeyi Wang, Xianlong Hong 2013

机译：BBE：三维互连电容与BEm块提取的分层计算*

The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance*

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