METHOD OF OPTIMIZING HIERARCHICAL VERY LARGE SCALE INTEGRATION (VLSI) DESIGN BY USE OF CLUSTER-BASED LOGIC CELL CLONING

摘要

A method of optimizing hierarchical very large scale integration (VLSI) design by use of cluster-based cell cloning. The method of the present invention provides improved yield or migration by reusing cells in order to reduce the number of unique instances of at least one of the reused cells. The method performs hierarchal optimization on the reduced set of clones (i.e., clusters). The method of the present disclosure includes, but is not limited to, the steps of setting the initial clustering parameters; assembling the physical design from existing reused cells; for each cell type, performing a full cloning operation in order to create a full set of duplicate cells; for each cell type, performing a full optimization of the design; for each cell type, performing an analyses of all cell environments and performing a clustering operation; and analyzing the overall results in order to determine whether the optimization objectives are achieved.