A MIMD-based video signal processing architecture suitable forlarge area integration and a 16.6-cm2 monolithicimplementation

摘要

The architecture and implementation of a programmable video signalnprocessor dedicated as building block of a multiple instruction multiplendata (MIMD)-based bus-connected multiprocessor system is presented. Thisnsystem can either be constructed from several single processor chips, ornit can be integrated on a large area integrated circuit containingnseveral processors. The processor allows an efficient implementation ofndifferent video coding standards like H.261, H.263, MPEG-1 and MPEG-2.nIt consists of a RISC processor supplemented by a coprocessor forncomputation intensive convolution-like tasks, which provides a peaknperformance of more than 1 giga-arithmetic operations per second (GOPS).nA large area integrated circuit integrating 9 processor elements (PE's)non an area of 16.6 cm2 has been designed. Due to yieldnconsiderations redundancy concepts have been implemented, that-even innthe presence of production defects-result in working chips utilizing anlower number of PE's. Each PE has built-in self-test (BIST)ncapabilities, which allow for an independent test of itself under thencontrol of its integrated fault-tolerant BIST controller. Defective PE'snare switched off. Only the PE's passing the BIST are used for videonprocessing tasks. Prototypes have been fabricated in a 0.8 Μmncomplementary metal-oxide-semiconductor (CMOS) process structured bynmasks using wafer stepping with overlapping exposures. Employingnredundancy, up to 6 PE's per chip were functional at 66 MHz, thusnproviding a peak arithmetic performance of up to 6 GOPS