A rated-clock test method for path delay faults

摘要

Current test generation algorithms for path delay faults assume anvariable-clock methodology for test application. Two-vector testnsequences assume that the combinational logic reaches a steady statenfollowing the first vector before the second vector is applied. Whilensuch tests may be acceptable for combinational circuits, their use fornnonscan sequential circuit testing is impractical. A rated-clock pathndelay simulator shows a large drop in coverage for vectors obtained fromnexisting test generators that assume a variable clock. A new testngeneration algorithm provides valid tests for uniform rated-clock testnapplication. In this algorithm, signals are represented for three-vectornsequences. The test generation procedure activates a target path fromninput to output using the three-vector algebra. For an effectivenbackward justification, we derive an optimal 41-valued algebra. This isnthe first time, rated-clock tests for large circuits are obtained.nResults for ISCAS-89 benchmarks show that rated-clock tests cover somenlongest, or close to longest, paths