Energy optimization of multilevel cache architectures for RISC andCISC processors

摘要

In this paper, we present the characterization and design ofnenergy-efficient, on chip cache memories. The characterization of powerndissipation in on-chip cache memories reveals that the memory peripheralninterface circuits and bit array dissipate comparable power. To optimizenperformance and power in a processor's cache, a multidivided modulen(MDM) cache architecture is proposed to conserve energy in the bit arraynas well as the memory peripheral circuits. Compared to a conventional,nnondivided, 16-kB cache, the latency and power of the MDM cache arenreduced by a factor of 1.9 and 4.6, respectively. Based on the MDM cachenarchitecture, the energy efficiency of the complete memory hierarchy isnanalyzed with respect to cache parameters in a multilevel processorncache design. This analysis was conducted by executing the SPECint92nbenchmark programs with the miss ratios for reduced instruction setncomputer (RISC) and complex instruction set computer (CISC) machines