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Pausible clocking-based heterogeneous systems

机译:基于可暂停时钟的异构系统

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This paper describes a novel communication scheme, which isnguaranteed to be free of synchronization failures, amongst multiplensynchronous and asynchronous modules operating independently. In thisnscheme, communication between every pair of modules is done through annasynchronous first-in first-out (FIFO) channel; communication between anmodule and the FIFO is done using a request/acknowledge handshaking.nSynchronization of handshake signals to the local module clock is donenin an unconventional way-the local clock built out of a ring oscillatornis paused or stretched, if necessary, to ensure that the handshakensignal satisfies setup and hold time constraints with respect to thenlocal clock. In order to validate this scheme, we implemented a testnchip in 0.5-Μm CMOS. This chip is designed as a ring, composed of twonsynchronous modules, an asynchronous module, and two asynchronous FIFOs.nEach module functions as a receiver to one module and a sender tonanother module. Test results show that the chip functions reliably up ton456 MHz
机译:本文介绍了一种新颖的通信方案,该方案可确保在独立运行的多个同步模块和异步模块之间没有同步失败。在此方案中,每对模块之间的通信都是通过异步先进先出(FIFO)通道完成的;模块和FIFO之间的通信使用请求/确认握手进行。n握手信号与本地模块时钟的同步以非常规的方式进行-由环形振荡器构建的本地时钟在必要时暂停或延长,以确保握手信号满足关于本地时钟的建立和保持时间限制。为了验证该方案,我们在0.5μmCMOS中实现了testnchip。该芯片设计为环形,由两个异步模块,一个异步模块和两个异步FIFO组成。每个模块分别充当一个模块的接收器和另一个模块的发送器。测试结果表明,该芯片在ton456 MHz频率下可可靠运行

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