Novel techniques for bus power consumption reduction inrealizations of sum-of-product computation

摘要

Novel techniques for power-efficient implementation of sum ofnproduct computation are presented. The proposed techniques aim atnreducing the switching activity required for the successive evaluationnof the partial products, in the busses connecting the storage elementsnwhere data and coefficients are stored to the functional units. This isnachieved through reordering the sequence of evaluation of the partialnproducts. Heuristics based on the traveling salesman problem arenproposed to perform the reordering for different categories ofnalgorithms. Information related to both data (dynamic) and coefficientsn(static) is used to drive the reordering. Experimental results from thenapplication of the proposed techniques on several signal-processingnalgorithms have proven that significant switching activity savings cannbe achieved