首页> 外国专利> Power reduction techniques for components in integrated circuits by assigning inputs to a plurality of ports based on power consumption ratings

Power reduction techniques for components in integrated circuits by assigning inputs to a plurality of ports based on power consumption ratings

机译:通过基于功耗额定值将输入分配给多个端口来降低集成电路组件的功耗的技术

摘要

Optimizing the power used in an integrated circuit. A circuit-level transformation/permutation reduces the power consumed by multipliers or other components in integrated circuits. Signals that toggle frequently are assigned to lower power multiplier ports or the number of times a signal changes value is minimized. Large width signals are assigned to the low power port. Large multipliers are divided up and optimized as above. Pipelined multipliers are used with registers so that signals change together.
机译:优化集成电路中使用的功率。电路级变换/置换减少了乘法器或集成电路中其他组件所消耗的功率。频繁切换的信号被分配给低功率乘法器端口,或者信号变化值的次数被最小化。大宽度的信号分配给低功率端口。大型乘法器如上所述进行了划分和优化。流水线乘法器与寄存器一起使用,以便信号一起改变。

著录项

  • 公开/公告号US7587620B1

    专利类型

  • 公开/公告日2009-09-08

    原文格式PDF

  • 申请/专利权人 AARON CHARLES EGIER;DAVID NETO;

    申请/专利号US20060431850

  • 发明设计人 AARON CHARLES EGIER;DAVID NETO;

    申请日2006-05-09

  • 分类号G06F1/32;G06F1;

  • 国家 US

  • 入库时间 2022-08-21 19:30:05

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号