首页>
外国专利>
Power reduction techniques for components in integrated circuits by assigning inputs to a plurality of ports based on power consumption ratings
Power reduction techniques for components in integrated circuits by assigning inputs to a plurality of ports based on power consumption ratings
展开▼
机译:通过基于功耗额定值将输入分配给多个端口来降低集成电路组件的功耗的技术
展开▼
页面导航
摘要
著录项
相似文献
摘要
Optimizing the power used in an integrated circuit. A circuit-level transformation/permutation reduces the power consumed by multipliers or other components in integrated circuits. Signals that toggle frequently are assigned to lower power multiplier ports or the number of times a signal changes value is minimized. Large width signals are assigned to the low power port. Large multipliers are divided up and optimized as above. Pipelined multipliers are used with registers so that signals change together.
展开▼