Reconfigurable pipelined 2-D convolvers for fast digital signalprocessing

摘要

In order to make software applications simpler to write and easiernto maintain, a software digital signal-processing library that performsnessential signal- and image-processing functions is an important part ofnevery digital signal processor (DSP) developer's toolset. In general,nsuch a library provides high-level interface and mechanisms, therefore,ndevelopers only need to know how to use algorithms, not the details ofnhow they work. Complex signal transformations then become functionncalls, e.g., C-callable functions. Considering the two-dimensional (2-D)nconvolver function as an example of great significance for DSP's, thisnpaper proposes to replace this software function by an emulation on anfield-programmable gate array (FPGA) initially configured by softwarenprogramming. Therefore, the exploration of the 2-D convolver's designnspace will provide guidelines for the development of a library ofnDSP-oriented hardware configurations intended to significantly speed upnthe performance of general DSP processors. Based on the specificnconvolver, and considering operators supported in the library asnhardware accelerators, a series of tradeoffs for efficiently exploitingnthe bandwidth between the general-purpose DSP and accelerators arenproposed. In terms of implementation, this paper explores thenperformance and architectural tradeoffs involved in the design of annFPGA-based 2-D convolution coprocessor for the TMS320C40 DSPnmicroprocessor available from Texas Instruments Incorporated. However,nthe proposed concept is not limited to a particular processor