Cost-effective VLSI architectures and buffer size optimization forfull-search block matching algorithms

摘要

This paper presents two efficient very large scale integrationn(VLSI) architectures and buffer size optimization for full-search blocknmatching algorithms. Starting from an overlapped data flow of searchnarea, both systolic- and semisystolic-array architectural solutions arenderived. By means of exploiting stream memory banks, not onlyninput/output (I/O) bandwidth can be minimized, but also processornelement efficiency can be improved. In addition, the controllernstructure for both solutions are very straightforward, making them verynsuitable for VLSI implementation to meet computational requirements.nMoreover, by exploring the dependency graph, we focus on the problem ofnreducing the internal buffer size under minimal I/O bandwidth constraintnto derive guidelines on reducing redundant internal buffer as well as tonachieve area-efficient VLSI architectures. Simulation results show that,nfor N=P=16 (N is the reference block size and P is the search range),nI/O bandwidth can be reduced by 2.4 times, while buffer size increasesnless than 38%. Two prototype chips for N=P=16 have been designed andnfabricated. Test results show that clock rate can be up to 90 MHz,nimplying that more than 87.9-K motion vectors per second can be achievednto meet real-time requirements specified in MPEG-2 MP@ML coding standard