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High-performance block-matching VLSI architecture with low memory bandwidth for power-efficient multimedia devices
High-performance block-matching VLSI architecture with low memory bandwidth for power-efficient multimedia devices
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机译:具有低存储带宽的高性能块匹配VLSI架构,适用于省电的多媒体设备
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摘要
A high-performance block-matching VLSI architecture with low memory bandwidth for power-efficient multimedia devices is disclosed. The architecture uses several current blocks with the same spatial address in different current frames to search the best matched blocks in the search window of the reference frame based on the best matching algorithm (BMA) to implement the process of motion estimation in video coding. The scheme of the architecture using several current blocks for one search window greatly increases data reuse, accelerates the process of motion estimation, and reduces the data bandwidth and the power consumption.
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