The memory/logic interface in FPGAs with large embedded memoryarrays

摘要

As the capacities of field-programmable gate arrays (FPGAs) grow,nthey will be used to implement much larger circuits than ever before.nThese larger circuits often require significant amounts of storage. Innorder to address these storage requirements, FPGAs with large embeddednmemory arrays are now being developed by several vendors. One of thencrucial components of an FPGA with on-chip memory is the routingnstructure between the memory arrays and logic resources. If thisnmemory/logic interface is not flexible enough, many circuits will benunroutable, while if it is too flexible, it will be slower and consumenmore chip area than is necessary. In this paper, we show that anninterconnect in which each memory pin can connect to between four andnseven logic routing tracks is best in terms of both area and speed. Wenalso show that by adding switches to support nets that connect multiplenmemory arrays, we can reduce the memory access time by up to 25% andnimprove the routability slightly