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The memory/logic interface in FPGAs with large embedded memory arrays

机译:具有大型嵌入式存储器阵列的FPGA中的存储器/逻辑接口

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As the capacities of field-programmable gate arrays (FPGAs) grow, they will be used to implement much larger circuits than ever before. These larger circuits often require significant amounts of storage. In order to address these storage requirements, FPGAs with large embedded memory arrays are now being developed by several vendors. One of the crucial components of an FPGA with on-chip memory is the routing structure between the memory arrays and logic resources. If this memory/logic interface is not flexible enough, many circuits will be unroutable, while if it is too flexible, it will be slower and consume more chip area than is necessary. In this paper, we show that an interconnect in which each memory pin can connect to between four and seven logic routing tracks is best in terms of both area and speed. We also show that by adding switches to support nets that connect multiple memory arrays, we can reduce the memory access time by up to 25% and improve the routability slightly.
机译:随着现场可编程门阵列(FPGA)容量的增长,它们将用于实现比以往更大的电路。这些较大的电路通常需要大量的存储空间。为了满足这些存储需求,一些供应商正在开发带有大型嵌入式存储器阵列的FPGA。带片上存储器的FPGA的关键组件之一是存储器阵列和逻辑资源之间的路由结构。如果此存储器/逻辑接口不够灵活,那么许多电路将无法路由,而如果过于灵活,它将变得较慢,并且消耗的芯片面积将超过所需的数量。在本文中,我们表明,从面积和速度两方面来看,每个内存引脚可以连接到四个至七个逻辑路由路径的互连是最佳的。我们还表明,通过添加交换机来支持连接多个内存阵列的网络,我们可以将内存访问时间减少多达25%,并略微提高可布线性。

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