Test generation and scheduling for layout-based detection of bridgefaults in interconnects

摘要

This paper presents a new approach to detecting faults inninterconnects; the novelty of the proposed approach is that testngeneration and scheduling are established using the physicalncharacteristics of the layout of the interconnect under test. Thisnincludes critical area extraction and a realistic fault model for anstructural methodology. Physical layout information is used to model thenadjacencies in an interconnect and possible bridge faults with anweighted graph, which is then analyzed to appropriately compact thentests and schedule their execution for (early) detection of bridgenfaults. Generation and compaction of the test vectors are accomplishednby calculating node and edge weight heuristics from the weightednadjacency graph. Simulation has been performed for unweighted andnweighted fault models. Results on random interconnects and the localninterconnect of a commercially available field-programmable gate arraynare provided. The advantage of the proposed approach is that, onnaverage, early detection of faults is possible using significantly fewerntests than with previous approaches. A further advantage is that itnrepresents a realistic alternative to adaptive testing because it avoidsncostly on-line test generation, while still having a small number ofnvectors