Design and optimization of dual-threshold circuits for low-voltagelow-power applications

摘要

Reduction in leakage power has become an important concern innlow-voltage, low-power, and high-performance applications. In thisnpaper, we use the dual-threshold technique to reduce leakage power bynassigning a high-threshold voltage to some transistors in noncriticalnpaths, and using low-threshold transistors in critical path(s). In ordernto achieve the best leakage power saving under target performancenconstraints, an algorithm is presented for selecting and assigning annoptimal high-threshold voltage. A general leakage current model whichnhas been verified by HSPICE simulations is used to estimate leakagenpower. Results show that the dual-threshold technique is good fornleakage power reduction during both standby and active modes. For somenISCAS benchmark circuits, the leakage power can be reduced by more thann80%. The total active power saving can be around 50% and 20% at low- andnhigh-switching activities, respectively