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Partitioning sequential circuits for pseudoexhaustive testing

机译:划分时序电路以进行伪穷举测试

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In this paper, we present an algorithm for partitioning sequential circuits. This algorithm is based on an analysis of a circuit's primary input cones and fanout values (PIFAN), and it uses a directed acyclic graph to represent the circuit. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. The feasibility and efficiency of our algorithm are evaluated by partitioning numerous standard digital circuits, including some large benchmark circuits containing up to 5597 gates. Our algorithm is based upon pseudoexhaustive testing methods where fault simulation is not required for test-pattern generation and grading; hence, engineering design time and cost are further reduced.
机译:在本文中,我们提出了一种划分时序电路的算法。该算法基于对电路的主要输入锥体和扇出值(PIFAN)的分析,并使用有向无环图来表示电路。采用侵入性方法,该方法通过自动插入可重新配置的测试单元和多路复用器来创建逻辑和物理分区。测试单元用于控制和观察多个划分点,而多路复用器扩展了测试单元提供的可控制性和可观察性。通过划分许多标准数字电路,包括包含多达5597个门的一些大型基准电路,来评估我们算法的可行性和效率。我们的算法基于伪穷举测试方法,在这种方法中,不需要进行故障仿真即可生成测试图案和进行评级;因此,工程设计时间和成本进一步减少。

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