Partitioning sequential circuits for pseudoexhaustive testing

摘要

In this paper, we present an algorithm for partitioning sequentialncircuits. This algorithm is based on an analysis of a circuit's primaryninput cones and fanout values (PIFAN), and it uses a directed acyclicngraph to represent the circuit. An invasive approach is employed, whichncreates logical and physical partitions by automatically insertingnreconfigurable test cells and multiplexers. The test cells are used toncontrol and observe multiple partitioning points, while the multiplexersnexpand the controllability and observability provided by the test cells.nThe feasibility and efficiency of our algorithm are evaluated bynpartitioning numerous standard digital circuits, including some largenbenchmark circuits containing up to 5597 gates. Our algorithm is basednupon pseudoexhaustive testing methods where fault simulation is notnrequired for test-pattern generation and grading; hence, engineeringndesign time and cost are further reduced