Low-power design of decimation filters for a digital IF receiver

摘要

This paper presents low-power design techniques at thenarchitectural level for design of decimation filters in a digital IFnreceiver for wide-area wireless data networks. A multimode decimationnfilter design implementing both Mobitex and Ardis networks is described.nThe power is reduced by a factor of 1422 and the area reduced by anfactor of 7.85 compared to an optimized single-mode two-stage design. Annew multistage decimation filter design tool is also presented, whichncompares alternative architectures on figures of merit which thenlow-power designer can map into technology-dependent area and powerncosts